Digi NS9750 Instrukcja Użytkownika Pobierz pdf (Strona 21)

System Memory interface signals

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Figure 4 shows NS9750B-A1 SDRAM clock termination.

Figure 4: SDRAM clock termination

clk_in

clk_out[0]

NS9750B-A1

clk_out[3]

clk_out[2]

CLK_IN

SDRAM Bank B

SDRAM Bank A

UNUSED_CLK

clk_out[1]

SDRAM_CLK[3]

SDRAM_CLK[2]

All series termination resistors

must be placed close to driver

Always connect clk_out[0] to clk_in

using series termination.

Must not drive any SDRAM loads.

Data in from SDRAMs is sampled on

the rising edge of this clock.

This trace can be a loop 2 to 3 inches in length.

Read data clock will be delayed 180pS/per inch.

Unused clk_outs are

terminated only

SDRAM banks have AC

termination placed at end

of traces

Address, data, and commands are

sampled by SDRAMs on the rising edge

of these clocks.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 87 88

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Digi NS9750 Instrukcja Użytkownika Strona 21