Digi NS9750 Instrukcja Użytkownika Pobierz pdf (Strona 59)

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SRAM timing

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       55

Static RAM write cycle

 WTWR = 0

WWEN = 0

 During a 32-bit transfer, all four byte_lane signals will go low.

 During a 16-bit transfer, two byte_lane signals will go low.

 During an 8-bit transfer, only one byte_lane signal will go low.

Note: If the PB field is set to 0, the byte_lane signals will function as write enable signals and the

we_n signal will always be high.

M22M21

M24M23

M22M21

M20M19

M18M17

M16M15

Note-1

clk_out<3:0>

data<31:0>

addr<27:0>

st_cs_n<3:0>

we_n

byte_lane<3:0>

byte_lane[3:0] as WE*

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 87 88

NS9750B-A1 Datasheet 1
Contents 3
NS9750B-A1 Datasheet 03/2006 4
NS9750B-A1 Features 5
2        6
System-level interfaces 8
System configuration 9
Table 2: PLL ND[4:0] 10
Pin name Configuration bits 10
General Purpose ID register 11
System boot 12
System Clock 13
NS9750B-A1 14
USB clock 15
System Memory interface 16
Pin # Signal Name 17
I/O Description 17
Name I/O Description 20
Ethernet interface 22
Clock generation/system pins 23
PCI interface 24
PCI/CardBus signals 26
24        28
GPIO MUX 29
Pin # Signal name 30
Table 12: GPIO MUX pinout 30
USB Power 35
Controller 35
CLSTN[0] 36
MLSTN[0] 36
CUSTN[0] 37
RED[0] 38
GREEN[0], BLUE[0] 38
C interface 39
USB Interface 39
Reserved pins 41
Address and register maps 42
BBus peripheral address map 43
Electrical characteristics 44
Maximum power dissipation 45
Typical power dissipation 45
DC electrical characteristics 46
USB DC electrical outputs 47
44        48
Power sequencing 49
Memory timing 50
SDRAM burst read (16-bit) 51
SDRAM burst write (16-bit) 52
SDRAM burst read (32-bit) 52
SDRAM burst write (32-bit) 53
SDRAM load mode 54
SDRAM refresh mode 54
Clock enable timing 54
SRAM timing 55
52        56
 WTWR = from 0 to 15 60
       57 61
58        62
Ethernet timing 63
Ethernet MII timing 64
Ethernet RMII timing 64
PCI timing 65
Internal PCI arbiter timing 66
64        68
C timing 69
LCD timing 70
68        72
LCD output timing 73
SPI timing 74
72        76
IEEE 1284 timing 77
USB timing 78
USB full speed load 79
USB low speed load 79
       80
JTAG timing 81
Clock timing 82
       79 83
Packaging 84
NS9750B-A1, 388 BGA 86
Product specifications 87

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